Why does FPGA configuration from HPS fail if there are unassigned IOs in an Agilex™ 7 SoC FPGA design?

Due to a known problem on Agilex™ 7 SoC FPGAs, the FPGA configuration (Phase 2) from HPS may fail in HPS's first boot mode if there are unassigned IOs in the design compiled in Quartus® Prime Pro and the Phase 2 bitstream is generated from a different compile.

Unassigned IOs can be randomly placed on available IO banks during compilation. If these are placed in available HPS shared GPIO banks, they may alter the HPS IO hash, resulting in a different Phase 2 bitstream compared to the Phase 1 bitstream.

For details on HPS shared GPIO banks, refer to the Agilex™ General-Purpose I/O and LVDS SERDES User Guide 

To workaround this problem, assign all IOs to defined locations or add dummy IO assignmnets.

This is scheduled to be fixed in a later release of Quartus® Prime Pro Edition Software.