Description
The Quartus® Prime Pro Edition Software version 24.1 provides limited hardware support for Agilex™ 5 IPs or features as per the table below. However, the device models, bitstreams, and firmware for the devices are not finalized.
Resolution
| Device Features/IP | IP/Functions Not Validated in Hardware for 24.1 | |
| Transceiver | GTS PMA/FEC Direct PHY Intel® FPGA IP GTS Reset Sequencer Intel® FPGA IP GTS System PLL Clocks Intel® FPGA IP | Example Design and FEC-Direct mode |
| GTS Transceiver Toolkit | FEC options | |
| Ethernet | GTS Ethernet Intel® FPGA Hard IP |
MII PCS only, PCS66 OTN, PCS66 FlexE mode,Example Design and Firecode FEC option |
| Low Latency 40G Ethernet Intel®FPGA IP | IP not validated in hardware | |
| Low Latency Ethernet 10G MAC Intel®FPGA IP | IP not validated in hardware | |
| 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP | IP not validated in hardware | |
| Triple-Speed Ethernet Intel® FPGA IP | IP not validated in hardware | |
| Ethernet Toolkit | PTP and FEC options | |
| PCIe | GTS AXI Streaming Intel® FPGA IP for PCI Express | Example design, atomic operation, multi-functions and virtualization, MSI 64-bit addressing, MSI-X Interrupts, PTM, AER, ECRC |
| CPRI | GTS CPRI PHY Intel®FPGA IP | IP not validated in hardware |
| Interlaken | GTS Interlaken Intel®FPGA IP | IP not validated in hardware |
| JESD204 | JESD204C GTS Intel®FPGA IP | IP not validated in hardware |
| Serial Lite IV | GTS Serial Lite IV Intel®FPGA IP | IP not validated in hardware |
| CSI | MIPI CSI -2 Intel®FPGA IP | IP not validated in hardware |
| PHYLITE | PHY Lite for parallel interfaces Intel®FPGA IP | IP not validated in hardware |
| EMIF | External Memory Interface Intel®FPGA IP | Please refer to EMIF Agilex™ 5 FPGA IP Release Notes |
| HPS | Processors and Peripherals | Please refer to Embedded software readiness |