Why does the Synopsys VCS* simulator produce incorrect simulation results for Agilex™ 5 FPGAs?

Agilex™ 5 FPGAs do not support the Synopsys VCS* two-step flow (compile and elaborate in one step and simulate in the next step). You might see incorrect simulation results when simulating a multi-IP design with Synopsys VCS simulator if you specify all IP and Quartus® simulation library source files using a single VCS command line, run_vcs.

Follow these steps to use Synopsys VCS* simulator with VCS MX flow:

1. Create design libraries using the mkdir command
2. Compile all IP and Quartus® simulation library source files into their respective libraries using vlogan or vhdlan commands
3. Elaborate the top-level design using the vcs command without specifying the source files compiled in Step 2
4. Simulate your design using the generated simv executable file

The above steps are sometimes referred to as VCS or VCS MX three-step flow (compile in one step, elaborate in the next step, and simulate in the final step).

Refer to the Platform Designer generated VCS MX simulation setup script (/synopsys/vcsmx/vcsmx_setup.sh) for the information on which library files to be compiled, command examples, and command arguments.

If you were previously using the Platform Designer generated VCS simulation setup script (/synopsys/vcs/vcs_setup.sh), switch to using the Platform Designer generated VCS MX simulation setup script (/synopsys/vcsmx/vcsmx_setup.sh).

Refer to Quartus® Prime Pro Edition User Guide: Third-party Simulation for more guidelines on incorporating the generated Synopsys VCS MX simulation scripts for use in a top-level project simulation setup script.