Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.3 and earlier, the CDR freeze feature for the GPON application does not function as expected when using F-Tile PMA/FEC Direct PHY Intel® FPGA IP.
To get the CDR freeze feature work, you need to:
1. Configure the F-Tile PMA/FEC Direct PHY Intel® FPGA IP GUI as follows:
- Set FGT PMA configuration rules as GPON
- Set the Adaptation mode as manual
- Enable fgt_rx_cdr_fast_freeze_sel port
- Enable fgt_rx_cdr_freeze port
2. After the design SOF file is programmed, enable the CDR freeze feature by setting the following two FGT registers:
- 0x62000[16] to 1'b1
- 0x62004[12] to 1'b1
Note that the above registers are only applicable to channels that are placed on Lane 0. For channels that are placed on other lanes, you need to add an offset address. For more details, please refer to F-Tile Architecture and PMA and FEC Direct PHY IP User Guide.
3. Drive the signals as follows:
- tie the fgt_rx_cdr_fast_freeze_sel signal to 1'b0
- assert the fgt_rx_cdr_freeze signal to 1'b1 when burst ends, and de-assert the fgt_rx_cdr_freeze signal to 1'b0 when burst starts
This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.