Beginning with the Quartus® Prime Pro Edition Software version 23.3, the Block Design Format (.BDF) has been deprecated. Any existing BDF design files must be converted to Verilog HDL or VHDL.
Convert your BDF files to Verilog HDL or VHDL using the Quartus® Prime Standard Edition command line with one of the following commands:
- quartus_map <project_name> --convert_bdf_to_verilog=<bdf_file_name>
- quartus_map <project_name> --convert_bdf_to_vhdl=<bdf_file_name>
This will generate a Verilog HDL or VHDL file in the same folder where the BDF file is located.
Some of the generated registers or instances may require renaming to work properly.
Notes:
The Quartus® Prime Standard Edition Software does not support devices newer than Arria® 10 FPGAs. For projects targeting newer device families, change the device to a supported one or create a dummy project targeting a supported device.
The Quartus® Prime Standard Edition Software does not support all the assignments that the Quartus® Prime Pro Edition Software supports. Comment out any unsupported assignments when converting your BDF to Verilog HDL or VHDL.