Can the setup timing slack be improved in the DCFIFOs used in the emulated true dual port (TDP) RAM by reducing the depth of the DCFIFOs when using an Stratix® 10 device?

Yes. You may see multiple setup timing violations in the DCFIFOs used in the emulated true dual port (TDP) RAM when using an Stratix® 10 device.

The setup timing violations may be observed from the nodes like the following:

• <path to your emulated TDP RAM instance>|ram_2port_0|fifo_wrapper_in|dcfifo_in|dcfifo_component|auto_generated|rdptr_g[<number>]
• <path to your emulated TDP RAM instance>|ram_2port_0|fifo_wrapper_out|dcfifo_out|dcfifo_component|auto_generated|ws_dgrp|dffpipe1|dffe3a[<number>]

Those setup timing slacks can be improved by reducing the depth of the DCFIFOs using the instructions shown in the Resolution below.

To reduce the depth of the DCFIFOs in the emulated TDP RAM, use the following steps.

1. Display the Hierarchy tab in the Project Navigator on the Quartus® Prime Pro Edition.
2. Expand your design hierarchy and find the following instances under the emulated TDP RAM instance.
       - ram_2port_0 > fifo_wrapper_in > dcfifo_in
       - ram_2port_0 > fifo_wrapper_out > dcfifo_out
3. Remember the entity names of the dcfifo_in instance and the dcfifo_out instance.
   In the following example figure, remember the entity names enclosed by the yellow square.
       - "ram2p_fifo_1910_sno4eky" for the instance dcfifo_in
       - "ram2p_fifo_1910_3zzux5y" for the instance dcfifo_out
   
4. Go to the Files tab of the Project Navigator.
5. Expand the .ip file of the emulated TDP RAM and find <the entity name of the dcfifo_in>.v and <the entity name of the dcfifo_out>.v.
   In the following example figure of the Files tab, the files enclosed by yellow square will be edited.
   
6. Open <the entity name of the dcfifo_in>.v.
7. Find the following parameters in the defparam declarations.
       - dcfifo_component.lpm_numwords  = <lpm_numwords number>
       - dcfifo_component.lpm_widthu  = <lpm_widthu number> 
   
8. Change dcfifo_component.lpm_numwords and dcfifo_component.lpm_widthu.
       -  dcfifo_component.lpm_numwords must be greater than the clock frequency ratio of clock B (fast clock) divided by clock A (slow clock) of the emulated TDP RAM IP
       -  dcfifo_component.lpm_numwords must be greater than 4
       -  dcfifo_component.lpm_numwords must be 2^dcfifo_component.lpm_widthu
   For example, 
       - If the ratio of Clock B frequency/Clock A frequency is 5, the minimum  dcfifo_component.lpm_numword must be 8 (2^3)
       - If  dcfifo_component.lpm_numword is 8 (2^3), dcfifo_component.lpm_widthu is 3
9. Save the file
10. Open <the entity name of the dcfifo_out>.v and repeat step 7 to 9

Please note that if the emulated TDP RAM IP is regenerated, the above files are regenerated and the parameters are restored to the default numbers too.