Article ID: 000074946 Content Type: Troubleshooting Last Reviewed: 02/14/2023

Why is there higher than expected FPGA resource utilization when instantiating the RAM: 2-Port Intel® FPGA IP with the Emulated TDP dual clock mode parameter enabled?

Environment

  • Intel® Quartus® Prime Pro Edition
  • RAM 2-PORT Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    When a RAM: 2-Port Intel® FPGA IP with the Emulated TDP dual clock mode parameter enabled is instantiated in the Intel® Quartus® Prime Software, you might see a higher-than-expected FPGA resource utilization when targeting Intel® Stratix® 10 devices. This is caused by the additional FIFOs implemented by the RAM: 2-Port Intel® FPGA IP.

    Resolution

    To work around this problem, perform the following steps:

    1. Navigate through the hierarchy and find the fifo_wrapper_in instance.
    2. Move on through the hierarchy until you come across the dcfifo_component instance.
    3. Reduce the value of the LPM_NUMWORDS and LPM_WIDTHU parameters. The value assigned for LPM_NUMWORDS must comply with the following equation: 2^LPM_WIDTHU. Make sure the FIFO depth is appropriate to support the data rate of your design.

    As an example:                

    dcfifo_component.lpm_numwords  = 16                

    dcfifo_component.lpm_widthu  = 4

    1. Repeat steps 1 to 3 for the fifo_wrapper_out instance.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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