Why does my 200GE or 400GE F-Tile Ethernet FPGA Hard IP Design Example with flow control enabled fail in the Quartus® Prime Pro - Support Logic Generation stage of compilation?

Due to a problem in the Quartus® Prime Pro Edition Software version 23.2, the 200GE or 400GE F-Tile Ethernet FPGA Hard IP Design Example will fail in the Support Logic Generation phase of compilation when the Stop TX traffic when link partner sends PAUSE parameter is set to Yes.

To workaround this problem, follow the steps below:

1. Locate and open the eth_f_hw_ip_top.sv file located in the <design_example_name>/hardware_test_design/common/ directory
2. Delete the i_tx_pfc and o_rx_pfc ports contained within the dut instance
3. Save the modified eth_f_hw_ip_top.sv file
4. Re-Compile the Design Example

This problem has been fixed in version 23.3 of the Quartus® Prime Pro Edition Software.