Why do I see an error when compiling the design example for F-Tile PMA/FEC Direct PHY Intel® FPGA IP?

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.4, when generating the design example, changing the board type to “ Intel Agilex® FPGA I-Series transceiver SoC Dev kit” will auto-pick AGIB027R31B1E2VR0 as the device OPN, and it causes the compilation error: "Attribute 'user.bb_f_ux_rx[0].bb.vsr_mode': Not a valid attribute name inside BCM 'ip_config_ux_rx".

Follow the steps below to work around this problem in the Intel® Quartus® Prime Pro Edition Software version 22.4.

For simulation test:

1. Use AGIB027R31B1E2V as the OPN under the Device tab before generating the example design
2. When generating the example design, under “Select Board,” please select None
3. Generate example design

For hardware test:

1. Use AGIB027R31B1E2V as the OPN under the Device tab before generating the example design
2. When generating the example design, under “Select Board,” please select None
3. Generate example design
4. Before compiling the design, copy all of the QSF settings from Intel® Quartus® Prime Pro Edition Software version 22.3 and update it in the generated QSF
5. "Tick the assembler" if not selected by default before starting compilation.

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.