Why does the 'Ethernet to CPRI' design example for the F-tile Dynamic Reconfiguration Suite Intel® FPGA IP fail to function in simulation when dynamically reconfiguring to the 25GE-1 profile?

Due to a problem in the Intel® Quartus®  Prime Pro Edition Software version 22.3, the testbench provided for the 'Ethernet to CPRI' design example for the F-tile Dynamic Reconfiguration Suite Intel® FPGA IP will fail to function correctly when dynamically reconfiguring to the 25GE-1 profile. This problem does not affect the design example when run on hardware.

To work around this problem in simulation, perform the following steps:

1. Navigate to <your example design directory>/example_testbench.
2. Open the file basic_avl_tb_top.sv in your preferred text editor. 
3. Locate the task eth_dr_to_25g and change the following lines:

   From
       // Step 6: Program DUT soft CSR
           $display ("** Info: Program DUT soft CSR ....");
           repeat (10) @(negedge i_reconfig_clk);
           avmm_write({8'b0, 24'h200}, {26'h0,6'h0});
           repeat (10) @(negedge i_reconfig_clk);
           avmm_write({8'b0, 24'h204}, {{20'b0},{3'b000},{3'b000},{3'b000},{3'b010}});
           repeat (10) @(negedge i_reconfig_clk);
           avmm_write({8'b0, 24'h208}, {28'h0,4'b000});
       

   To
       // Step 6: Program DUT soft CSR
           $display ("** Info: Program DUT soft CSR ....");
           repeat (10) @(negedge i_reconfig_clk);
           avmm_write({8'h10, 24'h200}, {26'h0,6'h0});
           repeat (10) @(negedge i_reconfig_clk);
           avmm_write({8'h10, 24'h204}, {{20'b0},{3'b000},{3'b000},{3'b000},{3'b010}});
           repeat (10) @(negedge i_reconfig_clk);
           avmm_write({8'h10, 24'h208}, {28'h0,4'b000});

4. Save the file.
5. Run the simulation using the provided scripts for your selected simulator.

This problem has been fixed starting in version 23.1 of the Intel® Quartus® Prime Pro Edition Software.