Article ID: 000092968 Content Type: Troubleshooting Last Reviewed: 05/19/2023

Why does the bar size in lspci log not match the configured size in the IP parameter when using Intel® Stratix® 10 H-Tile/L-Tile Avalon® Memory Mapped (AvalonMM) Hard IP for PCI Express*?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Avalon-MM Intel® Stratix® 10 Hard IP for PCI Express

    • OS Independent family

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    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2 and earlier, you may see bar size in lspci log doesn't match with the configured size in the IP parameter when using Intel® Stratix® 10 H-Tile/L-Tile Avalon® Memory Mapped (AvalonMM) Hard IP for PCI Express*.

     

     

    Resolution

    This problem is fixed in Intel® Quartus® Prime Pro Edition Software version 22.2 and onwards.

    Related Products

    This article applies to 4 products

    Intel® Stratix® 10 GX FPGA
    Intel® Stratix® 10 MX FPGA
    Intel® Stratix® 10 SX SoC FPGA
    Intel® Stratix® 10 TX FPGA

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