Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2, the “ptp_fw.tcl” script provided in the design examples for PTP variants of the F-tile Ethernet Intel® FPGA Hard IP might yield incorrect Tx or Rx tam_delta values. This problem only occurs when the scripts are run on the Windows operating system if the tam_delta value occupies more than 32 bits.
To work around this problem, perform the following steps:
1). Open the PTP firmware script located at <generated example design folder>/hardware_test_design/hwtest/altera/ptp/ptp_fw.tcl.
2). Find and replace the following lines of code:
a). From set bslip_p_dlpulse [format 0x%X ...
To set bslip_p_dlpulse [format 0x%lX ...
b). From set tx_tam_delta [format 0x%X [expr $tx_tam_n - $tx_tam_0]]
To set tx_tam_delta [format 0x%lX [expr $tx_tam_n - $tx_tam_0]]
c). From set tx_tam_delta [format 0x%X [expr $rx_tam_n + $billion_ns_fns - $tx_tam_0]]
To set tx_tam_delta [format 0x%lX [expr $tx_tam_n + $billion_ns_fns - $tx_tam_0]]
d). From set rx_tam_delta [format 0x%X [expr $rx_tam_n - $rx_tam_0]]
To set rx_tam_delta [format 0x%lX [expr $rx_tam_n - $rx_tam_0]]
e). From set rx_tam_delta [format 0x%X [expr $rx_tam_n + $billion_ns_fns - $rx_tam_0]]
To set rx_tam_delta [format 0x%lX [expr $rx_tam_n + $billion_nsfns - $rx_tam_0]]
f). From set rx_spulse_offset_0 [format 0x%X ...
To set rx_spulse_offset_0 [format 0x%lX ...
g). From set rx_spulse_offset_1 [format 0x%X ...
To set rx_spulse_offset_1 [format 0x%lX ...
3). Save the file.
This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition Software version 22.4.