Article ID: 000092461 Content Type: Troubleshooting Last Reviewed: 04/15/2024

Are there any known problems in the All Package Pins compilation report in the Quartus® Prime Pro Edition Software when targeting Agilex™ 7 devices?

Environment

    Intel® Quartus® Prime Pro Edition
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Description

Yes, when you compile a design targeting Agilex™ 7 devices using Quartus® Prime Pro Edition Software version 22.3 and earlier, the following issues will be seen in the All Package Pins compilation report :

1. The I/O direction of PWRMGT_SCL and PWRMGT_SDA are displayed as output.  However, this I/O direction is incorrect. They should be displayed as bidir.

2. The pin name of the SDM pin assigned to HPS_COLD_nRESET is displayed as HPS_COLD_RESET, and the I/O direction of this pin is displayed as output, However, this information is incorrect.  The pin name should be displayed as HPS_COLD_nRESET, and the I/O direction should be bidir.

Resolution

These problems are scheduled to be fixed in a future version of the Quartus® Prime Pro Edition Software.

Related Products

This article applies to 1 products

Intel Agilex® 7 FPGAs and SoC FPGAs

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