Why does my multi-instance design example for the F-tile Ethernet Intel® FPGA Hard IP fail to achieve link on an intermittent basis?

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.3, the reset logic for the multi-instance design example for the F-tile Ethernet Intel® FPGA Hard IP is improperly implemented. This leads to intermittent link failures upon initial bring-up of the design example. This problem exists for all multi-instance design examples, regardless of IP variant.

To work around this problem, perform the following steps:
 

1. Navigate to the <design example name>/hardware_test_design/ directory.
2. Open the eth_f_hw.v file. This is the top level of the design example.
3. Change the following line:

FROM:

assign rst_n[i] = arst;

TO:

assign rst_n[i] =  source_rst_n;

4. Compile the design example.

This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition Software version 22.4.