Yes, there are a few updates/changes to the final Intel® Stratix® 10 IBIS models, stratix10 models.xls (list of models), and stratix10_v3p0.ibs (IBIS file inside the stratix10.zip), which are listed below
1. In the stratix10 models.xls file, we have removed dsstl12, dpod12, sstl12, and pod12 IBIS model names with combination settings of p0 and s1 or p0 and on-chip termination (OCT).
This is because the models dsstl12, dpod12, sstl12, and pod12 are incorrectly listed with a pre-emphasis setting of 0 (p0). These I/O standards do not support the pre-emphasis setting of 0 when the slew rate is 1.
2. In the stratix10_v3p0.ibs file, we have added the sstl18ii_in_hps_lv IBIS model name under the [Pin] keyword.
This is because the sstl18ii_in_hps_lv model exists but is missing from the declare section under the [Pin] keyword.
3. in both the stratix10_v3p0.ibs and stratix10 models.xls files, we have removed the ‘p0’ setting from 1.2V, 1.5V, 1.8V, 2.5V, 3.0V LVCMOS, and 3.0V LVTTL IBIS model names.
This is because the models for 1.2V, 1.5V, 1.8V, 2.5V, 3.0V LVCMOS, and 3.0V LVTTL incorrectly contain the p0 setting. These I/O standards do not support the pre-emphasis feature.
4. In the stratix10 models.xls file, we have added the 1.8V LVCMOS IBIS models name supported for the HPS I/O bank.
This is because the 1.8V LVCMOS IBIS models name supported for HPS I/O bank are missing in the stratix10 models.xls file. The missing models are
The Intel® Stratix® 10 models.xls and stratix10_v3p0.ibs files will be corrected in a future revision.