Article ID: 000091592 Content Type: Error Messages Last Reviewed: 07/20/2022

Why does the Intel® Agilex™ FPGA EMIF Traffic Generator fail in Multirank DDR4 LRDIMM at higher operational frequency in the Intel® Quartus® Prime Pro Edition Software v21.2?

Environment

  • Intel® Quartus® Prime Design Software
  • Intel® FPGA Programming Software
  • Memory Models
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You might encounter bit errors at the start or end of BL8 burst at high frequency in Intel® Agilex™ device EMIF Traffic Generator. This failure occurs mainly due to inaccurate bus turnaround time settings.

    Resolution

    Intel® Agilex™ device EMIF Traffic Generator starts to pass after adding the additional bus turnaround time to the following parameters through EMIF IP GUI->controller Tab.  For example, + 3 cycles in the following parameters:


    rd_to_wr_same_chip

    wr_to_rd_same_chip

    rr_to_rd_diff_cihp

    rd_to_wr_diff_chip

    wr_to_wr_diff_chip

    wr_to_rd_diff_chip

    Additional information

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 1 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs

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