Why does the Intel Agilex® 7 FPGA EMIF Traffic Generator fail in Multirank DDR4 LRDIMM at a higher operational frequency in the Intel® Quartus® Prime Pro Edition Software v21.2?

You might encounter bit errors at the start or end of BL8 burst at high frequency in Intel Agilex® 7 device EMIF Traffic Generator. This failure occurs mainly due to inaccurate bus turnaround time settings.

Intel Agilex® 7 device EMIF Traffic Generator starts to pass after adding the additional bus turnaround time to the following parameters through EMIF IP GUI->controller Tab.  For example, + 3 cycles in the following parameters:

rd_to_wr_same_chip

wr_to_rd_same_chip

rr_to_rd_diff_cihp

rd_to_wr_diff_chip

wr_to_wr_diff_chip

wr_to_rd_diff_chip

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.