Article ID: 000091122 Content Type: Troubleshooting Last Reviewed: 01/11/2023

Why does the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example generation fail when using the Intel® Quartus® Prime Pro Edition Software version 22.1

Environment

  • Intel® Quartus® Prime Pro Edition
  • Interfaces
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The error "Error: can't read "rp_generated_name": no such variable" will be observed when generating the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example using the Intel® Quartus® Prime Pro Edition Software version 22.1.

    The error is caused by attempting to generate the design example with Example Design Files "Synthesis" option enabled, but the "Simulation" option is not enabled.

    Resolution

    To work around this problem ensure that both Simulation and Synthesis options are enabled before clicking the "Generate Example Design" button.

    This problem will be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 1 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs

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