Article ID: 000091098 Content Type: Error Messages Last Reviewed: 06/30/2022

Why do I receive an error message when running the TCL script for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Low Latency Ethernet 10G MAC Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.4.1 and later, the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example TCL script fails to run with the error message as shown below.

    error: open_service: Path  cannot be found

        while executing

    "open_service master $port_id"

        (procedure "reg_write" line 4)

        invoked from within

    "reg_write $PHY_IP_BASE_ADDR $PHY_USXGMII_CONTROL_REG [expr (($restart_an_value << $PHY_USXGMII_RESTART_AN) | ($speed_value << $PHY_USXGMII_SPEED) | ($..."

     

    Resolution

    To work around this problem in the Intel® Quartus® Prime Pro Edition Software version 21.4.1 and later, the hardware test TCL scripts need to be updated and the correct JTAG ID needs to be set during the hardware test.

    The steps are as shown below.

    1. Before the hardware test is started, replace the files and folders in <example_design>/LL10G_10G_USXGMII/hwtesting/system_console_fm using system-console-fm.zip.

    2. Initialize the design by running the command: source main.tcl

    3. A list of available JTAG masters is displayed. By default, the first JTAG master is selected. To select the JTAG master for Intel® Agilex™ devices targeted for Intel® Agilex™ I-Series FPGA Transceiver-SoC Dev Kit, run the command: set_jtag <JTAG Master>.

    Example: set_jtag 1

    4. The hardware test is ready to run for this design example.

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.

     

     

    Related Products

    This article applies to 1 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs

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