Article ID: 000090535 Content Type: Errata Last Reviewed: 05/14/2025

Why do I see the read data corruption with the Stratix® 10 FPGA QDRII+ IP when the calibration passes consistently?

Environment

    Intel® Quartus® Prime Pro Edition
    External Memory Interfaces Intel® Stratix® 10 FPGA IP
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Description

You might observe the read data corruption when there is a large difference in the calibrated DQS-en setting between calibration attempts with the Stratix® 10 FPGA QDRII+ intellectual property (IP).

Resolution

You can download the patch for Quartus® Prime Software v21.2 release to fix this problem. Please contact Altera support for other Quartus® Prime Software release patches.

Related Products

This article applies to 1 products

Intel® Stratix® 10 FPGAs and SoC FPGAs

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