Article ID: 000090306 Content Type: Troubleshooting Last Reviewed: 06/30/2022

Why dose FPGA masters fail to read from cache to get the latest value when FPGA-to-HPS interface CCU mode is used in Intel® Agilex™ 10 SX device?

Environment

  • Intel® SoC FPGA Embedded Development Suite (SoC EDS) Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    When using the FPGA-to-HPS interface in CCU mode, FPGA masters are expected to read from cache to get the latest value. But an issue may occur whereby FPGA masters are unable to get the latest value.  

    Resolution

    Cache coherency requires transactions from multiple masters having the same AxPROT value in ACE-lite interface, which defines the access permissions for read/write accesses.

    When HPS running in Linux(EL1) or ATF U-Boot(EL2) writes to or reads from HPS SDRAM, it refers to non-secure/privilege transactions. FPGA masters should use the same AxPROT value (b'011) to make sure it can read out the latest value from cache.

    When HPS running in ATF/SPL(EL3) or non-ATF U-Boot(EL3) writes to or reads from HPS SDRAM, it refers to secure/privilege transactions. FPGA masters should use the same AxPROT value (b'001) to make sure it can read out the latest value from cache.

    For more information on ACE-Lite protocol and AxPROT, please refer to

    https://developer.arm.com/documentation/ihi0022/e/AMBA-AXI3-and-AXI4-Protocol-Specification

    Related Products

    This article applies to 1 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs

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