Article ID: 000090176 Content Type: Errata Last Reviewed: 04/05/2022

Error: ../../../../pcie_ed_rp/ip/pcie_top/pcie/intel_rtile_pcie_ast_300/sim/pcie_intel_rtile_pcie_ast_300_mqi6v2a.sv(63124): Module 'rtile_s20_v0' is not defined

Environment

  • Intel® Quartus® Prime Pro Edition
  • Questa*-Intel® FPGA Edition
  • Interfaces
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.1 and earlier, the error below will be seen when using Questasim* Intel® FPGA Edition to simulate a design that instantiates the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express*.

    Error: ../../../../pcie_ed_rp/ip/pcie_top/pcie/intel_rtile_pcie_ast_300/sim/pcie_intel_rtile_pcie_ast_300_mqi6v2a.sv(63124): Module 'rtile_s20_v0' is not defined

    Resolution

    To work around this problem, use the Siemens* Questa* Advanced Simulator full version. This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Edition Software.

    Related Products

    This article applies to 1 products

    Intel® Agilex™ I-Series FPGAs and SoC FPGAs

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