Article ID: 000089524 Content Type: Connectivity Last Reviewed: 08/15/2023

Why does the Intel® Quartus Prime Pro Edition Software suggest connecting VREF pins to GND when implementing a DDR3 interface in Intel® Stratix® 10 devices?

Environment

  • Intel® Quartus® Prime Pro Edition
  • External Memory Interfaces Intel® Stratix® 10 FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description


    Starting from Intel® Quartus® Prime Pro Edition Software version 18.1, DDR3 IP implemented in Intel® Stratix® 10 devices will reference an internally generated VREF.

    Resolution

    The resepective VREF pins can be connected to GND

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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