When using “HPS First Configuration mode,” why does INIT_DONE stay LOW even after the Intel® Stratix® 10 device or Intel Agilex® 7 FPGA device enters user mode?

When using “HPS First Configuration mode” with Intel® Stratix® 10 or Intel Agilex® 7 FPGA devices and executing the SDM mailbox command “CONFIG_STATUS,” word 3 bit 1 will incorrectly report that the INIT_DONE status register is LOW, even after the external INIT_DONE signal goes HIGH  which indicates the FPGA has entered user mode successfully. This issue does not occur when using JTAG, ASx4, AVST configuration modes, or “FPGA First Configuration mode.”

The correct status of INIT_DONE can be verified by various methods, such as:

• Check the status of the INIT_DONE LED on the board, if available
• Read the CONFIG_STATUS using the Stratix 10 SDM Debug tool, and it only applies to Intel® Stratix® 10 FPGAs (because you are using the JTAG interface)
• Read the sdm_config_status command using the instructions available in AN 936: Executing SDM Commands via JTAG Interface

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.