Article ID: 000089483 Content Type: Troubleshooting Last Reviewed: 04/14/2022

When using “HPS First Configuration mode”, why does INIT_DONE stay LOW even after the Intel® Stratix® 10 device or Intel® Agilex™ device enters user mode?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    When using “HPS First Configuration mode”, and executing the SDM mailbox command “CONFIG_STATUS”, word 3 bit 1 will incorrectly report that the INIT_DONE status register is LOW, even after the external INIT_DONE signal goes HIGH and which indicates the FPGA enters the user mode was successful. This issue does not occur when using JTAG, ASx4, or AVST configuration, or when using “FPGA First Configuration mode”.

     

    The correct status of INIT_DONE can be verified by various methods such as:

    • Check the status of the INIT_DONE LED on the board, if available
    • Read the CONFIG_STATUS using the Stratix 10 SDM Debug tool, only applies to Intel® Stratix® 10 FPGAs (because you are using the JTAG interface)
    • Read the sdm_config_status command using the instructions available in AN 936: Executing SDM Commands via JTAG Interface
    Resolution

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.

     

     

    Related Products

    This article applies to 2 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs F-Series
    Intel® Stratix® 10 FPGAs and SoC FPGAs

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.