Why does the Interlaken (2nd Generation) Intel® FPGA IP fail to generate an evaluation mode programming file?

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.1, the Interlaken (2nd Generation) Intel® FPGA IP doesn't support the Intel® FPGA IP Evaluation Mode for time-limited programming file (.sof) generation.

To work around this problem, follow the steps below:

1. Download a copy of uflex_ilk_tx_ext.ocp and uflex_ilk_rx_regroup_n.ocp files
2. Place a copy of uflex_ilk_tx_ext.ocp under <IP_generation_folder>/altera_uflex_ilk_<xxxx>/synth/uflex_ilk_mac/
3. Place a copy of uflex_ilk_rx_regroup_n.ocp under <IP_generation_folder>/altera_uflex_ilk_<xxxx>/synth/uflex_ilk_regroup/
4. Add the lines below to the Intel® Quartus® Prime IP File of your IP variant <IP_generation_folder>/<IP_name>.qip
5. Recompile your design

* Remember to substitute <xxxx> with the four-digit number that was assigned to your IP variant after IP generation

This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software 21.2.