Article ID: 000089180 Content Type: Troubleshooting Last Reviewed: 03/23/2022

Why does my Intel® Agilex™ FPGA I/O PLL fail to lock or have high jitter after being reconfigured?

Environment

  • Intel® Quartus® Prime Pro Edition
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    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.4 and earlier, the Intel® Agilex™ FPGA I/O phase-locked loop (PLL) may fail or perform suboptimally on hardware after reconfiguration.
    This problem may occur when the reconfiguration .MIF is generated using the Platform Designer. The settings for bandwidth control, charge pump, and ripplecap are configured for Intel® Stratix® 10 devcies rather than for Intel® Agilex™ devices.
    This problem affects both I/O bank and fabric-feeding PLLs but does not affect other device families.

    Resolution

    To work around this problem, manually set the bandwidth control, charge pump, and rippecap settings according to the Intel® Agilex™ Clocking and PLL User Guide.
    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 1 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs

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