Article ID: 000088135 Content Type: Errata Last Reviewed: 02/14/2023

Why does the "o_rx_error" port of the E-Tile Hard IP for Ethernet Hard Intel® FPGA IP core not reflect oversized frames in transmission?

Environment

    Intel® Quartus® Prime Pro Edition
    E-tile Hard IP for Ethernet Intel® FPGA IP

OS Independent family

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Description

Due to a fault in the 100G E-Tile Hard IP for Ethernet Hard Intel® FPGA IP core RX status detection logic, you might observe oversized frames ( default maximum frame size in IP setting is 1518), fail to cause the relative bit of port o_rx_error to assert to reflect oversized frame behavior.

 

 

Resolution

There is no plan to fix this issue in future IP release. You can use statistic register(0x924/0x925) to monitor whether there is oversized frame in transmission.

Related Products

This article applies to 2 products

Intel Agilex® 7 FPGAs and SoC FPGAs F-Series
Intel® Stratix® 10 TX FPGA

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