Article ID: 000087931 Content Type: Troubleshooting Last Reviewed: 01/03/2023

Why does my F-Tile PMA/FEC Direct PHY Intel® FPGA IP design fail to merge TX Simplex and RX Simplex channel into the same physical channel when different PMA parallel clock frequency is detected between TX Simplex channel and RX Simplex channel ?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Transceiver PHY
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software v21.3, the TX simplex and RX simplex channel cannot be merged into the same physical transceiver channel when different parallel clock frequency is detected between the TX Simplex channel and RX Simplex channel.
    The parallel clock frequency is derived as:

     Parallel clock frequency = Data Rate / PMA Width

    There will be an error during the Support-Logic Generation stages. The error only happens when you use the PMA clocking mode. The system phase-locked loop (PLL) clocking mode is not affected by this problem.

    Resolution

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 1 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.