Why does my F-Tile PMA/FEC Direct PHY IP design fail to merge the TX Simplex and RX Simplex channels into the same physical channel when a different PMA parallel clock frequency is detected between the TX Simplex channel and the RX Simplex channel?

Due to a problem in the Quartus® Prime Pro Edition Software v21.3, the TX simplex and RX simplex channels cannot be merged into the same physical transceiver channel when a different parallel clock frequency is detected between the TX Simplex channel and RX Simplex channel.

The parallel clock frequency is derived as:

 Parallel clock frequency = Data Rate / PMA Width

An error will occur during the Support-Logic Generation stages. The error only occurs when you use the PMA clocking mode; the system phase-locked loop (PLL) clocking mode is not affected by this problem.

This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.