Article ID: 000087835 Content Type: Compatibility Last Reviewed: 01/10/2023

Can non-LVPECL clock buffer drive E-Tile Reference Clock input?

Environment

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Description

Using E-tile, the reference clock termination specifies LVPECL, but the actual IO standard used will vary depending on the clock buffer used. For instance, the Intel® Stratix® 10 TX Signal Integrity (SI) Development Kit has two different clock buffers for the E-Tile reference clocks: Silicon Labs Si53311 uses LVDS while Si5341 uses a customized differential output. The recommendation is to have the clock buffer output meet the differential voltage and common mode voltage requirements in the Intel® Stratix® 10 Device Datasheet:

Link to Table 68. E-Tile Reference Clock LVPECL DC Electrical Characteristics

Resolution

The guidelines in the Intel® Stratix® 10 Device Datasheet and the E-Tile Transceiver PHY User Guide are applicable even if a non-LVPECL IO standard is being used. Observe the voltage requirements and include the QSF settings.

Related Products

This article applies to 4 products

Intel® Agilex™ 7 FPGAs and SoC FPGAs F-Series
Intel® Stratix® 10 DX FPGA
Intel® Stratix® 10 MX FPGA
Intel® Stratix® 10 TX FPGA

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