Article ID: 000087813 Content Type: Troubleshooting Last Reviewed: 03/22/2023

Why does the Intel® FPGA P-Tile Avalon® Streaming IP for PCI Express design example targeting the Intel Agilex® 7 FPGA show minimum pulse width violations?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Example Application Avalon-Streaming Hard IP for PCI Express
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.2 and earlier, you might see minimum pulse width violations when using the design example for the Intel® FPGA P-Tile Avalon® Streaming IP for PCI Express targeting the Intel Agilex® 7 FPGA.

    Resolution

    This problem is fixed starting with the Intel® Quartus® Prime Edition Software 21.3.

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs F-Series

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