Why does the F-Tile PMA/FEC Direct PHY Intel® FPGA IP fail logic generation when the “Enable TX FGT PLL fractional mode” IP parameter is enabled for Intel Agilex® 7 I-series FPGAs in the Intel® Quartus® Prime Pro Edition Software version 21.2?

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.2, the F-Tile PMA/FEC Direct PHY Intel® FPGA IP may fail logic generation when the Enable TX FGT phase-locked loop (PLL) fractional mode intellectual property (IP) parameter is enabled for Intel Agilex® 7 I-series FPGAs.

When the Enable TX FGT PLL fractional mode IP parameter is enabled, the Intel® Quartus® Prime Pro Edition Software performs an incorrect validation using the integer mode reference clock frequency instead of the fractional mode reference clock frequency.

When this problem occurs, you might see the following error message:

Error(22465): Reference clock frequency of IP port '<path>|directphy_f_0|tx_pll_refclk_link[0]' (148.5000000 MHz) does not match the reference clock frequency of system clock IP port '<path>|systemclk_f_0|out_refclk_fgt_4' (140.0000000 MHz).

This problem is not seen when the integer mode reference clock frequency is the same as the fractional mode reference clock frequency.

You can work around this problem with the following options:

Option 1:

1. Upgrade your design to the Intel Quartus Prime Pro Edition Software version 21.3 or later.
2. Regenerate your F-Tile PMA/FEC Direct PHY Intel® FPGA IP.

Option 2:

1. In the Intel® Quartus® Prime Pro Edition Software version 21.2, open the F-Tile PMA/FEC Direct PHY Intel® FPGA IP generated .ip file.
2. Change the fgt_tx_pll_refclk_freq_mhz (TX FGT PLL integer mode reference clock) value to match the required fractional mode frequency.  An example shown below changes to 140 MHz.

766 <ipxact:parameter parameterId="fgt_tx_pll_refclk_freq_mhz" type="string">
767 <ipxact:name>fgt_tx_pll_refclk_freq_mhz</ipxact:name>
768 <ipxact:displayName>TX FGT PLL integer mode reference clock frequency</ipxact:displayName>
769 <ipxact:value>140.000000</ipxact:value>
770 </ipxact:parameter>
771 <ipxact:parameter parameterId="fgt_tx_pll_refclk_freq_itxt" type="string">
772 <ipxact:name>fgt_tx_pll_refclk_freq_itxt</ipxact:name>
773 <ipxact:displayName>TX FGT PLL fractional mode reference clock frequency</ipxact:displayName>
774 <ipxact:value>140.0</ipxact:value>

Option 3: 

1. Temporarily change the F-Tile PMA/FEC Direct PHY Intel FPGA IP data rate so that your desired TX FGT PLL integer mode reference clock frequency can be chosen. For example, a data rate of 14,000 Mbps permits a reference clock frequency of 140 MHz in integer mode.
2. Change the TX FGT PLL mode to fractional.
3. Change the data rate back to your desired data rate, for example, 11,880 Mbps.
4. Enter your desired 140 MHz TX FGT PLL fractional mode reference clock frequency again. 

This flow ensures the TX FGT PLL fractional and integer mode frequencies generated by the F-Tile PMA/FEC Direct PHY Intel® FPGA IP are the same.

This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.4.