Article ID: 000087667 Content Type: Error Messages Last Reviewed: 05/25/2022

Why does an internal error occur when using the Fast Register assignment on bidirectional pins of Intel® Agilex™ FPGA?

Environment

  • Intel® Quartus® Prime Pro Edition
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    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.3 and prior, you might observe an internal error when using bidirectional pins with Fast Input Register, Fast Output Register, or Fast Output Enable Register assignment. If any of the fast registers is enabled, you are required to enable all of them.

     

    An example of a failing case:

    Input register is assigned to Fast Input Register, but OE/Output registers are not assigned as Fast OE Register and Fast Output Register. The following internal error message is generated:

     

    Internal Error: Sub-system: U2B2_GENERIC, File: /quartus/db/u2b2_generic/u2b2_generic_translator.cpp, Line: 353

    Could not find a solution for pio_1_1

    Rule: fmgpio_reg::io_gpio_reg_rule @ pio_1_1.x0.fmio96_core_inst.fmio48tile_bot.x3.u1_0.x0.ioereg_top_5_.gpio_wrapper_0.gpio_reg pio_1_1.x0.fmio96_core_inst.fmio48tile_bot.x3.u1_0.x0.ioereg_top_5_.gpio_wrapper_0.gpio_reg.mode != BIDIR_MODE || pio_1_1.x0.fmio96_core_inst.fmio48tile_bot.x3.u1_0.x0.ioereg_top_5_.gpio_wrapper_0.gpio_reg.xio_gpio_ireg.mode != REG_MODE || pio_1_1.x0.fmio96_core_inst.fmio48tile_bot.x3.u1_0.x0.ioereg_top_5_.gpio_wrapper_0.gpio_reg.xio_gpio_oreg.mode inside {DDR_MODE_FR,SDR_MODE}

    Input variables and their values:

    pio_1_1.x0.fmio96_core_inst.fmio48tile_bot.x3.u1_0.x0.ioereg_top_5_.gpio_wrapper_0.gpio_reg.xio_gpio_ireg.mode == REG_MODE

    pio_1_1.x0.fmio96_core_inst.fmio48tile_bot.x3.u1_0.x0.ioereg_top_5_.gpio_wrapper_0.gpio_reg.xio_gpio_oreg.mode == COMBI_MODE

    pio_1_1.x0.fmio96_core_inst.fmio48tile_bot.x3.u1_0.x0.ioereg_top_5_.gpio_wrapper_0.gpio_reg.mode == BIDIR_MODE

     

    Resolution

    Option 1:

    Do not set any of the register to Fast * Register.

     

    Option 2:

    Assign all Input/OE/Output to Fast * Register. For example, add the following lines in the .qsf file:

    Input register packing: set_instance_assignment -name FAST_INPUT_REGISTER ON -to <path to register>

    Output register packing: set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to <path to register>

    Output enable register packing: set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to <path to register>

     

    Option 3:

    Use the following assignment to pack all the registers. Add the following line to the .qsf file:

    set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING “PACK ALL IO REGISTERS”

     

    This is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 1 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs

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