Article ID: 000087519 Content Type: Error Messages Last Reviewed: 02/23/2023

Why is the sys_error signal asserted high when using the Advanced SEU Detection Intel® FPGA IP in Intel® Stratix® 10 and Intel Agilex® 7 FPGA devices

Environment

    Intel® Quartus® Prime Pro Edition
    Advanced SEU Detection Intel® Stratix® 10 FPGA IP
    Advanced SEU Detection Intel® FPGA IP
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Description

Due to a problem in Intel® Quartus® Prime Pro Edition Software version 20.4 and above, you will observe the sys_error signal asserted high in Signal Tap Logic Analyzer as shown below when using the Advanced SEU Detection Intel® FPGA IP in Intel® Stratix® 10 and Intel Agilex® 7 FPGA devices.

 

The expected response of the sys_error signal should be low.    

 

 

Resolution

This problem is fixed starting with Intel® Quartus® Prime Pro Edition Software version 21.3.

 

 

Related Products

This article applies to 2 products

Intel Agilex® 7 FPGAs and SoC FPGAs
Intel® Stratix® 10 FPGAs and SoC FPGAs

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