Article ID: 000087219 Content Type: Troubleshooting Last Reviewed: 05/18/2013

Arria V and Cyclone V Hard IP for PCIe IP Core Do Not Cycle through Gen1 and Gen2 Data Rates in CBB Testing

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    When performing the TX Eye Test as part of the PCI Express Compliance Base Board (CBB) testing, the Arria V and Cyclone V Hard IP for PCIe do not cycle through the Gen1 and Gen2 data rates.

    Resolution

    This issue is fixed in version 13.0 of the Hard IP for PCI Express IP Cores.

    Related Products

    This article applies to 2 products

    Arria® V FPGAs and SoC FPGAs
    Cyclone® V FPGAs and SoC FPGAs

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