Article ID: 000087212 Content Type: Error Messages Last Reviewed: 05/12/2020

Error(15744): ( topology != EHIP_4CH_PTP_FEC )

Environment

  • Intel® Quartus® Prime Pro Edition
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    Description

    Due to a bug in the Intel® Quartus® Prime software version 19.4 and earlier, you may see the following Quartus Prime Fitter if instantiating two copies of the Intel E-Tile Hard IP for Ethernet Intel FPGA IP in Intel Stratix® 10 and Intel Agilex® transceiver E-Tile devices.

    Error(15653): The Fitter cannot find a legal configuration for the following atoms. Update any outdated transceiver PHY IP cores, correct any illegal pin assignments, and then recompile your design.
    Error(15744): In atom <path>|alt_ehipc3_0|alt_ehipc3_hard_inst|EHIP_CORE.c3_ehip_core_inst'
    Error(15744): The settings must match one or more of these conditions:
    Error(15744): ( topology != EHIP_4CH_PTP_FEC )

    You may see this error when the two Intel E-Tile Hard IP for Ethernet are configured for 100GbE with PTP and RSFEC enabled, and are constrained to adjacent PTP blocks.

    For example:

    • Two Intel E-Tile Hard IP for Ethernet configured for 100GbE with PTP and RSFEC enabled, constrained to use EHIP locations EHIP_CORE_0 and EHIP_CORE_1 may fail to fit
    • Two Intel E-Tile Hard IP for Ethernet configured for 100GbE with PTP and RSFEC enabled, constrained to use EHIP locations EHIP_CORE_2 and EHIP_CORE_3 may fail to fit
    • Two Intel E-Tile Hard IP for Ethernet configured for 100GbE with PTP and RSFEC enabled, constrained to use EHIP locations EHIP_CORE_0 and EHIP_CORE_2 may fit
    • Two Intel E-Tile Hard IP for Ethernet configured for 100GbE with PTP and RSFEC enabled, constrained to use EHIP locations EHIP_CORE_1 and EHIP_CORE_3 may fit
    Resolution

    This problem is fixed in Quartus Prime software version 20.1 and later.

    Related Products

    This article applies to 2 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs
    Intel® Agilex™ 7 FPGAs and SoC FPGAs

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