Article ID: 000087204 Content Type: Troubleshooting Last Reviewed: 11/24/2011

For DDR2 and DDR3 SDRAM Controller with UniPHY, Designs Without Leveling Fail in Stratix V Devices

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    If you target Stratix V devices with a IP core without leveling, the design fails.

    Resolution

    To work around this issue, disable the DM pins.The MegaWizard interface does not support design without leveling targeting Stratix V devices (the option is disabled), but you can generate a Stratix V design with leveling.

    Related Products

    This article applies to 1 products

    Stratix® V FPGAs

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