Simulation Fails for UniPHY External Memory Interfaces when Generating VHDL for Designs Using Nios II-based Sequencer

For designs using the Nios II-based sequencer, simulation can fail when generating VHDL output.

The workaround for this issue requires that you manually modify certain files:

1. Look for three .vhd files with file names beginning with a string similar to the following: dut_dut_e0_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module where <dut> is the name that you have specified for your project.
2. Open each of the three files in a text editor and add the following two lines to the beginning of each file: library altera_mf; use altera_mf.altera_mf_components.all;