Article ID: 000086984 Content Type: Troubleshooting Last Reviewed: 07/02/2013

Arria V Hard IP for PCI Express IP Core Timing Failure on Gen1 x8 Designs in 12.0 SP2

Environment

    Quartus® II Subscription Edition
BUILT IN - ARTICLE INTRO SECOND COMPONENT

Critical Issue

Description

Arria V Hard IP for PCI Express IP Core Gen1 x8 variants fail timing closure in version 12.0 SP2 of the Quartus II software.

Resolution

This issue is fixed in a version 12.1 of the Quartus II software.

Related Products

This article applies to 1 products

Arria® V FPGAs and SoC FPGAs

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