Article ID: 000086982 Content Type: Error Messages Last Reviewed: 08/21/2012

Critical warning: _p0_pin_map.tcl: Failed to find PLL clock for pins

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    For Arria®  V and Cyclone®  V Hard Memory Controller (HMC) designs, you will see the following critical warning if the MPFE clocks (mp_cmd_clk_0_clk, mp_rfifo_clk_0_clk, mp_wfifo_clk_0_clk) are generated by a stand-alone PLL and not the HMC PLL:

    Critical warning: <Instance_name>_p0_pin_map.tcl: Failed to find PLL clock for pins 

    Warning: <Instance_name>_p0_pin_map.tcl: Could not find all DRIVER CORE CK pins

    Resolution

    You need to apply the following workaround:

    Step 1)  Open the <Instance_name>_p0_pin_map.tcl file and change 

    if {[get_collection_size [get_registers -nowarn (driver_core_ck_pins)]] > 0} {


    with


    if {[string compare -nocase (driver_core_ck_pins) ""] != 0 && [get_collection_size [get_registers -nowarn (driver_core_ck_pins)]] > 0} {

    Step 2) In the <Instance_name>_p0.sdc file, change the pll_driver_core_clock to the clock that drives the MPFE clock inputs (mp_cmd_clk_0_clk, mp_rfifo_clk_0_clk, mp_wfifo_clk_0_clk).

    This issue will be fixed in a future release of the Quartus® II software.

     

    Related Products

    This article applies to 10 products

    Cyclone® V SX SoC FPGA
    Cyclone® V GT FPGA
    Cyclone® V GX FPGA
    Arria® V GX FPGA
    Arria® V SX SoC FPGA
    Arria® V GT FPGA
    Cyclone® V ST SoC FPGA
    Arria® V ST SoC FPGA
    Cyclone® V E FPGA
    Cyclone® V SE SoC FPGA

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