In version 12.0 of the Quartus II software, if you enable Multiple
packets per cycle in the Stratix V Hard IP for PCI Express
IP Core GUI, the following top-level ports change from one-bit to
Bit 1 of each two-bit vector
applies to the upper two qwords of data. Bit 0 of each vector applies
to the lower two qwords of data. The Stratix V Hard IP
for PCI Express User Guide defines these ports as one
This issue is fixed in version 12.0 SP1 of the Quartus II software..