Error: Internal error: (<signal name> => <signal name>) Internal error: standard logic: std_logic ports/signals must be width 1 but was <n>

Due to a problem in the Intel® Quartus® Prime Pro Edition software version 18.1 Update 1 and earlier, you may see this error when generating a Platform Designer system. This error occurs when the Platform Designer system includes a generic component.

To work around this problem, select the component in Platform Designer and then select the component instantiation tab. Change the width of each signal to 1, then revert the width back to its original value and generate the HDL.

This problem is scheduled to be fixed in a future release of the Intel Quartus Prime Pro Edition software.