Due to a problem in the Intel® Quartus® Prime software version 16.0 and later, you may see this error when you apply FAST_INPUT_REGISTER or FAST_OUTPUT_REGISTER or FAST_OUTPUT_ENABLE_REGISTER assignments for your design. The cause is in a processing of derive_pll_clocks constraint.
To avoid the error, follow below steps.
1: Comment out any "derive_pll_clocks" constraint from user SDC file
2: Run quartus_fit -plan
3: Un comment any "derive_pll_clocks" constraint from user SDC file
4: Run quartus_sta -s
4.1: Run project_open <project>
4.2: Run create_timing_netlist -snapshot planned (or -post_map if in standard edition)
4.3: Run read_sdc
4.4 Run write_sdc -expand expanded.sdc
5: Edit the expanded.sdc from step 4, remove all set_clock_uncertainly constraints
6: Edit QSF file, and replace original SDC with expanded.sdc in step 5
7: Run quartus_fit again
This problem was fixed in 18.1 version of the Intel® Quartus® Prime Pro edition software.