Article ID: 000086816 Content Type: Troubleshooting Last Reviewed: 08/12/2021

Why do the EMIF Efficiency Monitor counters “No readdatavalid Count” and “Master Write Idle Count” continue to incorrectly increment after traffic has completed?

Environment

    Intel® Quartus® Prime Pro Edition
    External Memory Interfaces Intel® Stratix® 10 FPGA IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a problem in the Intel® Quartus® Prime Pro Edition software version 20.4 and earlier, you may see the EMIF Efficiency Monitor counters “No readdatavalid Count” and “Master Write Idle Count” continue to incorrectly increment after the Traffic Generator 1.0 (TG1) has completed sending traffic and subsequently resetting the Efficiency Monitor status registers by clicking on the Clear Status Registers button.

Resolution

This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 21.1.

Related Products

This article applies to 2 products

Intel Agilex® 7 FPGAs and SoC FPGAs
Intel® Stratix® 10 FPGAs and SoC FPGAs

1

Need more help?

Contact support

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.