Article ID: 000086802 Content Type: Product Information & Documentation Last Reviewed: 07/22/2025

How can the data stored in the read data FIFO in the Stratix® 10 FPGA Serial Flash Mailbox Client IP core be read with a JTAG host?

Environment

    Intel® Quartus® Prime Pro Edition
    Mailbox Client Intel® Stratix® 10 FPGA IP
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Description

The read data FIFO can be accessed through the “rd_mem” bus in the Stratix® 10 FPGA Serial Flash Mailbox Client IP core. To read the data stored in the read data FIFO, you need to read data from the “rd_mem” bus. Refer to the IP rd_mem’s base and end address in the Platform Designer for the start address and the list of addresses you can read.

For more details about the read operation flow, refer to the Stratix® 10 FPGA Serial Flash Mailbox Client IP Core User Guide.

 

Resolution

For more details about the read operation flow, refer to the Stratix® 10 FPGA Serial Flash Mailbox Client IP Core User Guide.

Related Products

This article applies to 1 products

Intel® Stratix® 10 FPGAs and SoC FPGAs

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