Article ID: 000086791 Content Type: Troubleshooting Last Reviewed: 08/01/2017

Why does the fPLL in Arria 10 devices not lock when the 'Enable phase alignment' option is turned on?

Environment

  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • fPLL Intel® Arria® 10 Cyclone® 10 FPGA IP
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    Description

    In Arria® 10 devices, initial fPLL calibration may fail when the ‘Enable phase alignment’ option is turned on when the fPLL is in ‘core mode’.

    The reason for this behavior is that the fPLL's output C counters are not released from reset upon power-up at the same time as the feedback M counter. The initial calibration happens after the feedback counter is released, but before the output counters. So, the initial calibration fails since 'Enable phase alignment' uses the C1 counter as the feedback counter.

    Resolution

    To work around this you need to recalibrate the fPLL. This requires adding the reconfiguration port to the fPLL and then doing reads/writes to specific register locations using the following steps:
    1) Modify the design to enable fPLL reconfiguration
    2) Create logic in the core that does the following :
    a) Write 0x1 to bit [0] in address 0x126 of the fPLL.  This will cause the fPLL to select internal feedback
    b) Write 0x1 to bits [1] in address 0x100 of the fPLL and then 0x01 to address 0x000 of the fPLL to request PreSICE to recalibrate the fPLL.  fPLL recalibration must be done when internal feedback is selected.
    c) Monitor bit 1 of address 0x280 of the fPLL and wait until the bit changes to 0x0.  This indicates recalibration is completed.
    d) Write 0x0 to bit [0] in address 0x126 of the fPLL.  This causes the fPLL to select feedback compensation mode.
    e) Monitor the fPLL lock signal or bit [0] of address 0x280 of the fPLL and wait until the fPLL locks

    These steps are also covered in PLL Feedback and Cascading Clock Network section in the Arria® 10 Transceiver PHY user guide.

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