Article ID: 000086761 Content Type: Troubleshooting Last Reviewed: 06/08/2018

Why does my downstream IOPLL fail to lock when cascading IOPLLs in Intel® Stratix® 10 devices?

Environment

Bug ID: FB: 528586;

Quartus Edition

Intel® Quartus® Prime Pro Edition

Version Found: 18.0

FPGA Intellectual Property

IOPLL Intel® FPGA IP

Version Found: 18.0

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Description

When cascading IOPLLs in Intel® Stratix® 10 devices, if the downstream IOPLL has calibrated before the upstream IOPLL or if the upstream IOPLLs calibration has failed, this may cause cause the downstream IOPLL not to lock.

Resolution

Connect the permit_cal input of the downstream IOPLL to the locked output of the upstream IOPLL when cascading IOPLLs to prevent the downtream IOPLL calibrating before the upstream IOPLL has completed calibration and has locked to its incoming clock.

Description
Resolution

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