Article ID: 000086755 Content Type: Troubleshooting Last Reviewed: 03/23/2022

Why are there compilation errors in the VHDL design example for Intel® Agilex™ EMIF IP when using the Cadence NCSim* or the Cadence Xcelium* simulators?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Memory Interfaces and Controllers
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition software version 21.2 and earlier, you may see similar errors below when compiling the VHDL design example for Intel® Agilex™ EMIF IP in the Cadence NCSim* or the Cadence Xcelium* simulators.

    ncelab: *E,CFEPLM (sim/ip/ed_sim/ed_sim_emif_cal/altera_emif_cal_iossm_210/sim/ed_sim_emif_cal_altera_emif_cal_iossm_210_cohzsbq_arch.sv,15|60): Foreign module port calbus_rdata_1 of mode in must be associated with port/signal of entity/component ED_SIM_EMIF_CAL_ALTERA_EMIF_CAL_IOSSM_210_COHZSBQ_ARCH (sim/ip/ed_sim/ed_sim_emif_cal/altera_emif_cal_iossm_210/sim/ed_sim_emif_cal_altera_emif_cal_iossm_210_cohzsbq.vhd: line 65, position 66).

    ncelab: *E,CFEPLM (sim/ip/ed_sim/ed_sim_emif_cal/altera_emif_cal_iossm_210/sim/ed_sim_emif_cal_altera_emif_cal_iossm_210_cohzsbq_arch.sv,15|60): Foreign module port calbus_seq_param_tbl_1 of mode in must be associated with port/signal of entity/component ED_SIM_EMIF_CAL_ALTERA_EMIF_CAL_IOSSM_210_COHZSBQ_ARCH (sim/ip/ed_sim/ed_sim_emif_cal/altera_emif_cal_iossm_210/sim/ed_sim_emif_cal_altera_emif_cal_iossm_210_cohzsbq.vhd: line 65, position 66).

    Resolution

    This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software v21.3.

    Related Products

    This article applies to 1 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs

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