The Intel Agilex® 7 FPGA PHYLite simulation example design with dynamic reconfiguration enabled should show an example of dynamic reconfiguration working by changing the interpolator delay via the traffic stimuli. However, due to a problem in the Intel® Quartus® Prime Pro Edition Software version 20.4, the traffic stimuli in the Intel Agilex® 7 FPGA PHYLite simulation example design does not send any traffic to the calibration IP if the PHYLite group is set to Input pin type because the interpolator phase is set to a hardcoded value.
Note: This problem does not occur if the PHYLite group is set to Output pin type or Bidirectional pin type.
To work around this problem in the Intel® Quartus® Prime Pro Edition Software version 20.4, the interpolator phase must not be a hardcoded value, which requires making some modifications to the phylite_tester.sv and test_logic_iossm.sv files to allow the traffic stimuli to read the interpolator phase, increment the read value, then modify the interpolator phase to the new value.
Perform the following changes to the file named “phylite_tester.sv”:
1. Line #159: Remove state declaration PHASE DELAY and add two states declaration: CORE_PHASE_DELAY and IO_PHASE_DELAY
2. Line #177: Change from
assign iossm_test_start = (prbs_fsm == PHASE_DELAY);
to
assign iossm_test_start = (prbs_fsm == CORE_PHASE_DELAY);
3. Line #323: Change the prbs_fsm signal in INIT state from
prbs_fsm <= (CHANNEL_PIN_TYPE == "INPUT") ? IO_DRIVE : ((IOSSM_TEST_EN == 1) ? PHASE_DELAY : CORE_DRIVE);
to
prbs_fsm <= (IOSSM_TEST_EN == 1) ? (CHANNEL_PIN_TYPE == "INPUT" ? IO_PHASE_DELAY : CORE_PHASE_DELAY) : (CHANNEL_PIN_TYPE == "INPUT" ? IO_DRIVE : CORE_DRIVE);
4. Line #338: Change the prbs_fsm signal in IO_CHECK state from
prbs_fsm <= (CHANNEL_PIN_TYPE == "OUTPUT") ? ((IOSSM_TEST_EN == 1) ? PHASE_DELAY : CORE_DRIVE) : IO_DRIVE;
to
prbs_fsm <= (IOSSM_TEST_EN == 1) ? (CHANNEL_PIN_TYPE == "OUTPUT" ? CORE_PHASE_DELAY : IO_PHASE_DELAY) : (CHANNEL_PIN_TYPE == "OUTPUT" ? CORE_DRIVE : IO_DRIVE);
5. Line #338: Change the prbs_fsm signal in CORE_CHECK state from
prbs_fsm <= (CHANNEL_PIN_TYPE == "INPUT") ? IO_DRIVE : ((IOSSM_TEST_EN == 1) ? PHASE_DELAY : CORE_DRIVE);
to
prbs_fsm <= (IOSSM_TEST_EN == 1) ? (CHANNEL_PIN_TYPE == "INPUT" ? IO_PHASE_DELAY : CORE_PHASE_DELAY) : (CHANNEL_PIN_TYPE == "INPUT" ? IO_DRIVE : CORE_DRIVE);
6. Line #341: Remove
PHASE_DELAY: begin
if (core_checker_failed | io_checker_failed)
prbs_fsm <= CHECKER_FAILED;
else if (iossm_phase_shift_done)
prbs_fsm <= CORE_DRIVE;
end
and replace with these two:
IO_PHASE_DELAY: begin
if (core_checker_failed | io_checker_failed)
prbs_fsm <= CHECKER_FAILED;
else if (iossm_phase_shift_done)
prbs_fsm <= IO_DRIVE;
end
CORE_PHASE_DELAY: begin
if (core_checker_failed | io_checker_failed)
prbs_fsm <= CHECKER_FAILED;
else if (iossm_phase_shift_done)
prbs_fsm <= CORE_DRIVE;
end
Perform following changes to file named “test_logic_iossm.sv”:
1. Line #43: Change the value of IOSSM_INIT_PIN_DELAY to 196
2. After line #45: Add local parameter declaration:
localparam WAIT_INTERVAL = 8;
3. Line #59: Add these three following states declaration after IOSSM_WAIT_REQ
IOSSM_PRE_READ,
IOSSM_PRE_RDATA,
IOSSM_PRE_WAIT,
4. Line #72: Change from
if (!reset_n) begin
pin_dly_write <= IOSSM_INIT_PIN_DELAY;
prev_pin_dly_write <= IOSSM_INIT_PIN_DELAY;
end else if (cal_debug_write && !cal_debug_waitrequest)begin
prev_pin_dly_write <= pin_dly_write;
pin_dly_write <= pin_dly_write IOSSM_DELAY_STEP;
end
to
if (!reset_n) begin
pin_dly_write <= 0;
prev_pin_dly_write <= 0;
end else if (cal_debug_read_data_valid && iossm_fsm == IOSSM_PRE_RDATA) begin
prev_pin_dly_write <= cal_debug_read_data[IOSSM_PIN_DELAY_WIDTH-1:0] IOSSM_DELAY_STEP;
pin_dly_write <= cal_debug_read_data[IOSSM_PIN_DELAY_WIDTH-1:0] IOSSM_DELAY_STEP;
end
5. Line #85: Change from
end else if (cal_debug_read_data_valid) begin
to
end else if (cal_debug_read_data_valid && iossm_fsm == IOSSM_RDATA) begin
6. Line #108: Change iossm_fsm signal in IOSSM_INIT state from
iossm_fsm <= IOSSM_WRITE;
to
iossm_fsm <= IOSSM_PRE_READ;
7. After IOSSM_INIT state, add these two following states:
IOSSM_PRE_READ: begin
if (!cal_debug_waitrequest)
iossm_fsm <= IOSSM_PRE_RDATA;
end
IOSSM_PRE_RDATA: begin
if (cal_debug_read_data_valid)
iossm_fsm <= IOSSM_WRITE;
end
8. Line #139: Change from
assign cal_debug_read = iossm_fsm == IOSSM_READ;
to
assign cal_debug_read = (iossm_fsm == IOSSM_READ) || (iossm_fsm == IOSSM_PRE_READ);
9. Line #146: Change from
assign wait_done = (req_wait_interval == 7) ? 1 : 0;
to
assign wait_done = (req_wait_interval == WAIT_INTERVAL-1) ? 1 : 0;
This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.1.