Article ID: 000086682 Content Type: Product Information & Documentation Last Reviewed: 04/04/2017

How do I resolve IO_AUX and RST_SRC_ID fitter errors when the Quartus Prime project contains Arria 10 External Memory Interfaces IP ?


  • Intel® Quartus® Prime Pro Edition
  • External Memory Interfaces Intel® Arria® 10 FPGA IP

    Incorrect Arria® 10 EMIF IP global_reset_n port signal connections or enabling In System Sources and Probes (ISSP) can cause fitter errors of these types :

    Error (12934): Fitter was unable to place an EMIF/PHYLite system

    Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 IO_AUX(s)).

    Error (175020): The Fitter cannot place logic IO_AUX that is part of Arria 10 External Memory Interfaces ed_synth_altera_emif_<value> in region <value> to <value>, to which it is constrained, because there are no valid locations in the region for logic of this type.
    Error (175005): Could not find a location with: RST_SRC_ID of <value> (1 location affected)


    Common causes of these error messages and their resolutions are shown below:

    1) The Quartus® Prime project contains multiple external memory interfaces which are placed in I/O Banks in the same I/O column but have different reset signals connected to their global_reset_n ports.

    Resolution : Multiple interfaces placed in I/O Banks in the same I/O column must have a common reset signal connected to their global_reset_n ports.

    2) The Quartus Prime project has ALTERA_EMIF_ENABLE_ISSP enabled. This typically occurs if there are multiple Arria 10 EMIF example designs instantiated in the project.
    An example qsf file constraint is
    set_global_assignment -name VERILOG_MACRO "ALTERA_EMIF_ENABLE_ISSP=1"

    Resolution : Remove the above qsf constraint and do not select the Arria 10 External Memory Interfaces IP Diagnostics tab -> Example Design -> Enable In-system-sources-and-probes option.

    If a fitter error is still seen after following the guidance shown above, check that the memory interface signals meet the pin placement guidelines.
    A recommended starting point is to use minimal placement constraints and let the Quartus fitter place the rest of the interface signals before refining the pinout later.

    The recommended minimal placement constraints are:

    • One address signal, the PLL reference clock, and the RZQ pin in the I/O Bank chosen for the address/command signals.
    • DQS signals in the I/O Banks chosen for the memory data bus signals.

    For further information on pin placement, refer to these sections in the External Memory Interfaces Handbook:
    Volume 2 Chapter 1 - Guidelines for Arria 10 External Memory Interface IP
    Volume 3 Chapter 2 - Examples of External Memory Interface Implementations for DDR4 (similar rules apply for other memory interface protocols).

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs