Article ID: 000086668 Content Type: Error Messages Last Reviewed: 11/14/2024

Fatal: (vsim-3817) Port "configupdate" of entity "system_altpll_0" is not in the component being instantiated.

Environment

    Intel® Quartus® Prime Standard Edition

All

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a problem in the Quartus® Prime Standard Edition Software version 18.1 and earlier, you may see Fatal Error message mentioned above when simulating VHDL based simulation model of ALTPLL FPGA IP.

Resolution

To work around this problem, update simulation script to use the IP top level wrapper file from <ip name>/synthesis/ directory instead of <ip name>/simulation/ directory.

Related Products

This article applies to 12 products

Arria® II FPGAs
Intel® MAX® 10 FPGAs
Cyclone® II FPGA
Cyclone® IV FPGAs
Cyclone® FPGAs
Stratix® II FPGAs
Cyclone® III FPGAs
Arria® GX FPGA
Intel® Cyclone® 10 LP FPGA
Stratix® FPGAs
Stratix® IV FPGAs
Stratix® III FPGAs

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