Article ID: 000086665 Content Type: Troubleshooting Last Reviewed: 06/14/2021

Can we connect single-ended output clock generated from ALTPLL which is configured in "zero-delay buffer mode" to a PLL_CLKOUTn pin of Intel® MAX® 10 FPGA?


  • Quartus® II Subscription Edition

    No. Due to hardware restriction, when ALTPLL of Intel® MAX® 10 FPGA is configured in zero-delay buffer (ZDB) mode and the output clock is assigned to a PLL_CLKOUTn pin that is configured as single-ended I/O standard, user will encounter following error:

    Error (176557): Can't place  PLL "pll_inst:pll_inst_inst|altpll:altpll_component|pll_inst_altpll:auto_generated|pll1" in target device due to device constraints

    Error (176593): Cannot place  PLL "pll_inst:pll_inst_inst|altpll:altpll_component|pll_inst_altpll:auto_generated|pll1" in PLL location PLL_1 -- compensated output clock pin "<output_pin_of_PLL>" of the PLL must be placed in dedicated output clock I/O -- PLL is in zero-delay buffer mode

    Error (176568): Can't place  PLL "pll_inst:pll_inst_inst|altpll:altpll_component|pll_inst_altpll:auto_generated|pll1" in PLL location PLL_1 because I/O cell <output_pin_of_PLL>(port of type CLK of the PLL) has an incompatible location assignment with PLL I/O pin Pin_xx.


    This restriction is applicable only to the zero-delay buffer mode in ALTPLL.


    Connect the ATLPLL output clock to PLL_CLKOUTp pin.

    The Intel® MAX® 10 Clocking and PLL User Guide is scheduled to be updated with this detail in a future release.

    Related Products

    This article applies to 1 products

    Intel® MAX® 10 FPGAs